The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 18, 2025

Filed:

Jan. 20, 2023
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventor:

Alexei Vladimirovich Bourd, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06T 15/30 (2011.01); G06T 17/00 (2006.01); G06T 17/10 (2006.01);
U.S. Cl.
CPC ...
G06T 15/30 (2013.01); G06T 17/005 (2013.01); G06T 17/10 (2013.01); G06T 2210/12 (2013.01); G06T 2210/21 (2013.01);
Abstract

Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may obtain an indication of a BVH structure associated with a view frustum, where the BVH structure includes at least one first-level BVH including a plurality of first-level nodes and a plurality of second-level BVHs including a plurality of second-level nodes. The apparatus may also calculate whether the view frustum intersects with each first-level bounding box in the at least one first-level BVH. Further, the apparatus may calculate, for each first-level bounding box that the view frustum intersects, whether the view frustum intersects with each first-level child nod that is associated with each first-level bounding box. The apparatus may also output an indication of all of the first-level child nodes that the view frustum intersects for each of the set of first-level bounding boxes that the view frustum intersects.


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