The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 18, 2025

Filed:

May. 16, 2023
Applicant:

Battelle Memorial Institute, Columbus, OH (US);

Inventors:

Adam G. Kimura, Westerville, OH (US);

Andrew S. Elliott, Columbus, OH (US);

Daniel A. Perkins, Lewis Center, OH (US);

Assignee:

BATTELLE MEMORIAL INSTITUTE, Columbus, OH (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/323 (2020.01); G06F 30/327 (2020.01); G06F 30/33 (2020.01); G06F 117/06 (2020.01);
U.S. Cl.
CPC ...
G06F 30/323 (2020.01); G06F 30/327 (2020.01); G06F 30/33 (2020.01); G06F 2117/06 (2020.01); H01J 2237/31798 (2013.01);
Abstract

A Register Transfer Level (RTL) representation is recovered from a netlist representing an integrated circuit (IC). The netlist is converted to a graph comprising nodes belonging to a set of node types and edges connecting the nodes. The set of node types includes an instance node type representing an electronic component and a wire node type representing signal transfer between components. The graph is converted to a standardized graph by replacing subgraphs of the graph with standardized subgraphs. An RTL representation of the standardized graph is generated by operations including building signal declarations in a hardware description language (HDL) from the wire nodes of the standardized graph and building signal assignments in the HDL from instance nodes of the standardized graph.


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