The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 18, 2025

Filed:

Jan. 19, 2023
Applicant:

Sambanova Systems, Inc., Palo Alto, CA (US);

Inventors:

Arnav Goel, Palo Alto, CA (US);

Neal Sanghvi, Palo Alto, CA (US);

Jiayu Bai, Palo Alto, CA (US);

Qi Zheng, Palo Alto, CA (US);

Ravinder Kumar, Palo Alto, CA (US);

Assignee:

SambaNova Systems, Inc., Palo Alto, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/16 (2006.01); G06F 12/1036 (2016.01);
U.S. Cl.
CPC ...
G06F 12/1036 (2013.01); G06F 13/1668 (2013.01); G06F 2212/657 (2013.01);
Abstract

A heterogeneous processing system including a host processor coupled to a host memory, a first processor coupled to a first memory, a second processor coupled to a second memory, multiple data transfer resources, and switch and bus circuitry that communicatively couples the host processor, the first processor, the second processor, and the data transfer resources. The host processor is configured to detect an application for execution by both the first processor and the second processor, to select one of multiple data transfer methods for transferring data between the first and second processors, and to configure the heterogeneous processing system based on the selected data transfer method. The data transfer methods include memory extension operation, one memory to memory transfer operation, and two memory to memory transfer operation using at least one intermediate host buffer.


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