The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 18, 2025

Filed:

Apr. 20, 2022
Applicant:

Siltronic Corporation, Portland, OR (US);

Inventors:

Andrei Istratov, Portland, OR (US);

Tom Wu, Vancouver, WA (US);

Katharina Zahnweh, Burghausen, DE;

Assignee:

SILTRONIC CORPORATION, Portland, OR (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B24B 49/02 (2006.01); B24B 9/06 (2006.01); B28D 5/00 (2006.01);
U.S. Cl.
CPC ...
B24B 49/02 (2013.01); B24B 9/065 (2013.01); B28D 5/0064 (2013.01);
Abstract

A method for processing a silicon wafer, the method including cutting an ingot to form a wafer, extracting from measured shape data a cross-sectional profile, the cross-sectional profile passing through the center of the wafer and being aligned with a cutting direction of an ingot, interpolating the shape data with a fixed and pre-determined step size, fitting a first second-degree polynomial to the cross-sectional profile, determining a residual profile by subtracting the polynomial from the cross-sectional profile, fitting a second second-degree polynomial to the residual profile using a sliding window of pre-determined width to determine a position, height, and curvature of each peak and valley of the residual profile, determining a waviness parameter based on the position, height, and curvature of each peak and valley of the residual profile, and further processing the wafer based on the waviness parameter and a predetermined waviness threshold.


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