The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 11, 2025
Filed:
Aug. 17, 2021
Applicant:
Nuvolta Technologies (Hefei) Co., Ltd., Hefei, CN;
Inventors:
Jinbiao Huang, Nashua, NH (US);
John Lin, Carlsbad, CA (US);
Assignee:
Nuvolta Technoloiges (Heifei) Co., Ltd., Hefei, CN;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/762 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/00 (2006.01); H01L 29/78 (2006.01); H03K 17/687 (2006.01);
U.S. Cl.
CPC ...
H03K 17/687 (2013.01); H01L 21/76205 (2013.01); H01L 21/76224 (2013.01); H01L 21/823481 (2013.01); H01L 27/088 (2013.01); H01L 29/00 (2013.01); H01L 29/7816 (2013.01);
Abstract
An apparatus includes a first drain/source region and a second drain/source region over a substrate, and a first gate adjacent to the first drain/source region, a second gate adjacent to the second drain/source region and a third gate between the first gate and the second gate, wherein the first drain/source region, the second drain/source region, the first gate, the second gate and the third gate form two back-to-back connected transistors.