The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 11, 2025

Filed:

Feb. 28, 2023
Applicant:

Lumileds Llc, San Jose, CA (US);

Inventors:

Tze Yang Hin, Cupertino, CA (US);

Anantharaman Vaidyanathan, San Jose, CA (US);

Srini Banna, San Jose, CA (US);

Ronald Johannes Bonne, Plainfield, IL (US);

Assignee:

LUMILEDS, LLC, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/48 (2006.01); F21S 41/153 (2018.01); F21V 23/00 (2015.01); F21Y 105/10 (2016.01); F21Y 105/16 (2016.01); F21Y 115/10 (2016.01); H01L 21/683 (2006.01); H01L 23/00 (2006.01); H01L 25/16 (2023.01); H01L 27/15 (2006.01); H01L 33/62 (2010.01);
U.S. Cl.
CPC ...
H01L 21/4853 (2013.01); F21S 41/153 (2018.01); F21V 23/002 (2013.01); H01L 21/486 (2013.01); H01L 21/6835 (2013.01); H01L 24/19 (2013.01); H01L 24/81 (2013.01); H01L 24/82 (2013.01); H01L 25/167 (2013.01); H01L 27/156 (2013.01); H01L 33/62 (2013.01); F21Y 2105/10 (2016.08); F21Y 2105/16 (2016.08); F21Y 2115/10 (2016.08); H01L 2221/68345 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/24225 (2013.01); H01L 2224/8112 (2013.01); H01L 2224/81192 (2013.01); H01L 2224/81815 (2013.01); H01L 2224/82815 (2013.01); H01L 2924/12041 (2013.01); H01L 2933/0041 (2013.01); H01L 2933/0066 (2013.01);
Abstract

Systems are described. A system includes a silicon backplane having a top surface, a bottom surface, and side surfaces and a substrate surrounding the side surfaces of the silicon backplane. The substrate has a top surface, a bottom surface and side surfaces. At least one bond pad is provided on the bottom surface of the substrate. A metal layer is provided on the bottom surface of the substrate and the bottom surface of the silicon backplane and has a first portion electrically and thermally coupled to the bottom surface of the silicon backplane in a central region and second portions that extend between a perimeter region of the silicon backplane and the at least one bond pad. An array of metal connectors is provided on the top surface of the silicon backplane.


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