The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 11, 2025

Filed:

Jul. 23, 2021
Applicants:

Chengdu Boe Optoelectronics Technology Co., Ltd., Chengdu, CN;

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Binyan Wang, Beijing, CN;

Cong Liu, Beijing, CN;

Tianyi Cheng, Beijing, CN;

Feng Wei, Beijing, CN;

Meng Li, Beijing, CN;

Shiqian Dai, Beijing, CN;

Kaipeng Sun, Beijing, CN;

Lina Wang, Beijing, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/3266 (2016.01); G02F 1/133 (2006.01); G09G 3/32 (2016.01); G09G 3/36 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
G09G 3/3266 (2013.01); G02F 1/133 (2013.01); G09G 3/32 (2013.01); G09G 3/36 (2013.01); G09G 2300/0408 (2013.01); G09G 2300/0426 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01); H01L 27/12 (2013.01);
Abstract

A display substrate and a display apparatus are disclosed. The display substrate includes a base substrate including a display region and a peripheral region located on at least one side of the display region, and a first gate drive circuit, the first gate drive circuit includes a first clock signal line, a second clock signal line and N shift register units that are cascaded; each shift register unit of the N shift register units includes a first output circuit; the first output circuit includes the first output transistor, the orthographic projection of the second clock signal line on the base substrate is located between an orthographic projection of the first output transistor on the base substrate and the orthographic projection of the first clock signal line on the base substrate. The display substrate can reduce load of the first clock signal line and the second clock signal line.


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