The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 11, 2025

Filed:

Jun. 04, 2021
Applicant:

Arm Limited, Cambridge, GB;

Inventors:

Supreet Jeloka, Austin, TX (US);

Mudit Bhargava, Austin, TX (US);

Saurabh Pijuskumar Sinha, Schertz, TX (US);

Rahul Mathur, Austin, TX (US);

Assignee:

Arm Limited, Cambridge, GB;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/16 (2006.01); G06F 9/30 (2018.01);
U.S. Cl.
CPC ...
G06F 17/16 (2013.01); G06F 9/30014 (2013.01); G06F 9/30036 (2013.01); G06F 9/30032 (2013.01);
Abstract

According to one implementation of the present disclosure, a method includes performing a spatial alignment of at least one of first or second data tiers of a circuit; and performing a computation based on the spatial alignment of the at least one of the first and second data tiers. According to another implementation of the present disclosure, a circuit includes: a compute circuitry; and at least first and second data tiers of two or more data tiers positioned at least partially overlapping one another. In an example, each of the at least first and second data tiers is coupled to the compute circuitry. In certain implementations, the positioning of the first and second data tiers at least partially overlapping one another corresponds to a spatial alignment.


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