The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 11, 2025

Filed:

May. 13, 2021
Applicants:

Hefei Boe Display Technology Co., Ltd., Anhui, CN;

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Chunxu Zhang, Beijing, CN;

Yuntian Zhang, Beijing, CN;

Xiaoting Jiang, Beijing, CN;

Haipeng Yang, Beijing, CN;

Ke Dai, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/1345 (2006.01); G02F 1/1333 (2006.01); G02F 1/1335 (2006.01); G02F 1/1362 (2006.01); G09G 3/36 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
G02F 1/13454 (2013.01); G02F 1/133388 (2021.01); G02F 1/136286 (2013.01); H01L 27/1255 (2013.01); G02F 1/133512 (2013.01); G09G 3/3674 (2013.01); G09G 2300/0426 (2013.01); G09G 2310/0286 (2013.01);
Abstract

Provided is an array substrate. The array substrate includes: a base substrate; a plurality of clock lines; a plurality of clock leads; a plurality of shift register units; and a compensation capacitor plate, disposed on the base substrate and in the peripheral region, wherein the compensation capacitor plate is connected to the clock lead, and the compensation capacitor plate and the clock lead are in different layers, an area of the compensation capacitor plate being negatively correlated with a length of the clock lead connected to the compensation capacitor plate.


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