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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12219763 B1

PDFFull Text
Date of Patent:
Feb. 04, 2025

Filed:

May. 13, 2022

Integrated circuit device

Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jisung Cheon, Ansan-si, KR;

Byunggon Park, Seoul, KR;

Joowon Park, Seoul, KR;

Sangjun Hong, Hwaseong-si, KR;

Jinsoo Lim, Yongin-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, KR;

Attorney:

Muir Patent Law, PLLC

Primary Examiner:

Christopher A Johnson

Int. Cl.
CPC ...
H10B 43/27 (2023.01); H01L 21/28 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/535 (2006.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/35 (2023.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); H01L 21/76805 (2013.01); H01L 21/76816 (2013.01); H01L 21/76877 (2013.01); H01L 21/76895 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/535 (2013.01); H01L 29/40114 (2019.08); H01L 29/40117 (2019.08); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/35 (2023.02);
Abstract

An integrated circuit device including a substrate having a cell and interconnection region; and a first stacked structure and a second stacked structure on the first stacked structure, each of the first and second stacked structures including insulating layers and word line structures that are alternately stacked one by one on the substrate in the cell region and the interconnection region, wherein, in the interconnection region the first stacked structure includes a first dummy channel hole penetrating through the first stacked structure, the second stacked structure includes a second dummy channel hole communicatively connected to the first dummy channel hole, the second dummy channel hole penetrating through the second stacked structure, respectively, and a first dummy upper width of an uppermost end of the first dummy channel hole is greater than a second dummy upper width of an uppermost end of the second dummy channel hole.

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