The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 04, 2025
Filed:
Aug. 11, 2021
Applicant:
SK Hynix Inc., Icheon-si Gyeonggi-do, KR;
Inventors:
Won Geun Choi, Icheon-si Gyeonggi-do, KR;
Jung Shik Jang, Icheon-si Gyeonggi-do, KR;
Jang Won Kim, Icheon-si Gyeonggi-do, KR;
Mi Seong Park, Icheon-si Gyeonggi-do, KR;
Assignee:
SK hynix Inc., Icheon-si Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 43/27 (2023.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 43/10 (2023.01); H10B 63/00 (2023.01); H10B 41/20 (2023.01); H10B 99/00 (2023.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 43/10 (2023.02); H10B 63/34 (2023.02); H10B 41/20 (2023.02); H10B 99/00 (2023.02);
Abstract
There are provided a memory device and a manufacturing method of the memory device. The memory device includes: a first gate stack structure and a second gate stack structure, disposed on a substrate; and a slit disposed between the first gate stack structure and the second gate stack structure to electrically isolate the first gate stack structure and the second gate stack structure from each other.