The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 04, 2025

Filed:

Jun. 19, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Oblesh Jinka, Stamford, CT (US);

Salvatore Bernardo Olivadese, Stamford, CT (US);

Sean Hart, Tarrytown, NY (US);

Nicholas Torleiv Bronn, Long Island City, NY (US);

Jerry M. Chow, White Plains, NY (US);

Markus Brink, White Plains, NY (US);

Patryk Gumann, Tarrytown, NY (US);

Daniela Florentina Bogorin, Syracuse, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H05K 7/20 (2006.01); G06F 30/20 (2020.01); G06N 10/00 (2022.01); H01L 21/265 (2006.01); H01L 23/31 (2006.01); H01L 23/32 (2006.01); H01L 31/02 (2006.01); F28D 21/00 (2006.01); G06F 113/20 (2020.01);
U.S. Cl.
CPC ...
H05K 7/20372 (2013.01); G06F 30/20 (2020.01); G06N 10/00 (2019.01); H01L 21/26593 (2013.01); H01L 23/3107 (2013.01); H01L 23/3114 (2013.01); H01L 23/32 (2013.01); H01L 31/0201 (2013.01); F28D 2021/0028 (2013.01); G06F 2113/20 (2020.01);
Abstract

A thermalization structure is formed using a cover configured with a set of pillars, the cover being a part of a cryogenic enclosure of a low temperature device (LTD). A chip including the LTD is configured with a set of cavities, a cavity in the set of cavities having a cavity profile. A pillar from the set of pillars and corresponding to the cavity has a pillar profile such that the pillar profile causes the pillar to couple with the cavity of the cavity profile within a gap tolerance to thermally couple the chip to the cover for heat dissipation in a cryogenic operation of the chip.


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