The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 04, 2025

Filed:

Apr. 25, 2023
Applicant:

Guangzhou Tyrafos Semiconductor Technologies Co., Ltd, Guangzhou, CN;

Inventors:

Ping-Hung Yin, Taipei, TW;

Jia-Shyang Wang, Miaoli County, TW;

Jai-Jyun Shen, New Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N 25/78 (2023.01); G06F 1/08 (2006.01); H01L 25/075 (2006.01); H01L 25/18 (2023.01); H01L 27/146 (2006.01); H03K 19/0185 (2006.01); H03L 7/099 (2006.01); H04N 25/60 (2023.01); H04N 25/627 (2023.01); H04N 25/63 (2023.01); H04N 25/709 (2023.01); H04N 25/76 (2023.01); H04N 25/77 (2023.01); H04N 25/772 (2023.01); H04N 25/778 (2023.01);
U.S. Cl.
CPC ...
H04N 25/78 (2023.01); G06F 1/08 (2013.01); H01L 25/0753 (2013.01); H01L 25/18 (2013.01); H01L 27/14612 (2013.01); H01L 27/14632 (2013.01); H01L 27/14636 (2013.01); H03K 19/018521 (2013.01); H03L 7/099 (2013.01); H04N 25/60 (2023.01); H04N 25/627 (2023.01); H04N 25/63 (2023.01); H04N 25/709 (2023.01); H04N 25/77 (2023.01); H04N 25/772 (2023.01); H04N 25/778 (2023.01); H04N 25/7795 (2023.01);
Abstract

Disclosed are a chip with automatic clock signal correction and an automatic correction method. The chip includes a transmission interface, an oscillator and a correction logic circuit. The transmission interface provides a first clock signal. The oscillator generates a second clock signal. The correction logic circuit is coupled to the oscillator and the transmission interface, and performs correction operation to count the first clock signal to generate a first clock count value, and count the second clock signal to generate a second clock count value. When the first clock count value is equal to the first count target value, the correction logic circuit stops counting, and calculates a correction value based on the second clock count value and the second count target value. The correction logic circuit outputs the correction value to the oscillator, and the oscillator corrects a frequency of the second clock signal according to the correction value.


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