The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 04, 2025

Filed:

Dec. 08, 2023
Applicant:

Psemi Corporation, San Diego, CA (US);

Inventors:

Kashish Pal, Reading, GB;

Emre Ayranci, Costa Mesa, CA (US);

Miles Sanner, San Diego, CA (US);

Assignee:

pSemi Corporation, San Diego, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03F 1/02 (2006.01); H03F 1/22 (2006.01); H03F 1/26 (2006.01); H03F 3/193 (2006.01); H03F 3/68 (2006.01); H04L 27/26 (2006.01);
U.S. Cl.
CPC ...
H03F 1/223 (2013.01); H03F 1/26 (2013.01); H03F 3/193 (2013.01); H03F 3/68 (2013.01); H04L 27/2647 (2013.01); H03F 1/0277 (2013.01); H03F 2200/294 (2013.01); H03F 2200/489 (2013.01);
Abstract

An amplifier circuit configuration capable of processing non-contiguous intra-band carrier aggregate (CA) signals using amplifiers is disclosed herein. In some cases, each of a plurality of amplifiers is an amplifier configured as a cascode (i.e., a two-stage amplifier having two transistors, the first configured as a 'common source' input transistor, e.g., input field effect transistor (FET), and the second configured in a “common gate” configuration as a cascode output transistor, (e.g. cascode output FET). In other embodiments, the amplifier may have additional transistors (i.e., more than two stages and/or stacked transistors). The amplifier circuit configuration can be operated in either single mode or split mode. A switchable coupling is placed between the drain of the input FETs of each amplifier within the amplifier circuit configuration. During split mode, the coupling is added to the circuit to allow some of the signal present at the drain of each input FET to be coupled to the drain of the other input FET.


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