The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 04, 2025
Filed:
Feb. 20, 2024
Murata Manufacturing Co., Ltd., Kyoto, JP;
Gregory Szczeszynski, Hollis, NH (US);
Murata Manufacturing Co., Ltd., San Diego, CA (US);
Abstract
Circuits and methods for protecting a multi-level power converter using no more than two high-voltage FET switches while allowing all or most other power switches to be low-voltage FET switches. Some embodiments provide protective high-voltage top and bottom FETs designed to saturate before the remaining low-power FET switches saturate. Other embodiments may use only low-power FETs for the power switches but provide protective circuits configured to be in an always-ON (conducting) state when in normal power conversion operation, and to quickly switch to an OFF (non-conducting) state in the event of transients or a fault condition. Optionally, one or more of the protective circuits may be used in a controlled manner to limit or block current flow during certain types of fault conditions and/or to limit in-rush current during startup of a power converter.