The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 04, 2025

Filed:

Nov. 03, 2023
Applicant:

Georgia Tech Research Corporation, Atlanta, GA (US);

Inventors:

Nelson Estacio Lourenco, Atlanta, GA (US);

Adilson Silva Cardoso, Atlanta, GA (US);

Moon-Kyu Cho, Atlanta, GA (US);

Christopher Timothy Coen, Atlanta, GA (US);

John D. Cressler, Atlanta, GA (US);

Douglas Robert Denison, Atlanta, GA (US);

William B. Hunter, Atlanta, GA (US);

Ickhyun Song, Atlanta, GA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03F 1/18 (2006.01); H01P 5/16 (2006.01); H03F 3/04 (2006.01); H03H 11/32 (2006.01); H03K 19/173 (2006.01);
U.S. Cl.
CPC ...
H01P 5/16 (2013.01); H03F 3/04 (2013.01); H03H 11/32 (2013.01); H03K 19/173 (2013.01); H03F 2200/294 (2013.01);
Abstract

A transversal radio frequency filter circuit having a low noise amplifier connected along an input signal path, a first power divider connected between the low noise amplifier and four single taps, and an output path connected to the outputs of each of the four single taps. Each of the four single taps having a coefficient control mechanism, a polarity selection mechanism, and a time delay element. The coefficient control mechanism can include a wideband digital step attenuator configured to support high control range of the coefficient. Additionally, the circuit can include a second power divider connected between the outputs of each of the four single taps and the output path. The circuit can further include a field-programmable gate array configured to control coefficient control mechanisms, the polarity selection mechanisms, and the time delay elements (when they are variable time delay elements).


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