The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 04, 2025

Filed:

Feb. 25, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Inhyo Hwang, Asan-si, KR;

Young Lyong Kim, Anyang-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 23/49822 (2013.01); H01L 24/16 (2013.01); H01L 24/17 (2013.01); H01L 25/0652 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/17181 (2013.01); H01L 2224/17183 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06562 (2013.01);
Abstract

Provided is a semiconductor package including a first semiconductor chip provided on a package substrate, an interconnection substrate provided on the package substrate, the interconnection substrate having a side surface facing the first semiconductor chip, and a second semiconductor chip provided on the interconnection substrate and extended to a region on a top surface of the first semiconductor chip, wherein the interconnection substrate includes a lower interconnection layer facing the package substrate, an upper interconnection layer facing the first semiconductor chip, and a passive device between the lower interconnection layer and the upper interconnection layer, and wherein the passive device is electrically connected to the second semiconductor chip.


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