The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 04, 2025

Filed:

Mar. 07, 2023
Applicant:

Wenzhou University, Zhejiang, CN;

Inventors:

Gang Li, Zhejiang, CN;

Hui Li, Zhejiang, CN;

Pengjun Wang, Zhejiang, CN;

Xilong Shao, Zhejiang, CN;

Hao Ye, Zhejiang, CN;

Assignee:

Wenzhou University, Zhejiang, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 9/32 (2006.01); G06F 21/75 (2013.01);
U.S. Cl.
CPC ...
G06F 21/75 (2013.01); H04L 9/3278 (2013.01);
Abstract

A machine learning attack resistant strong PUF with a dual-edge sampling function comprises switch units, a first arbiter and a second arbiter. The first arbiter is for determining a sequential order of delays at a rising edge of signals input to a first input terminal and a second input terminal of the first arbiter. The second arbiter is for determining a sequential order of delays at a falling edge of signals input to a first input terminal and a second input terminal of the second arbiter. Each switch unit is composed of eight MOS transistors. The strong PUF has a high capacity to resist machine learning attacks and small hardware expenditure through simple structural design of the switch units, realizing machine learning attack resistance and small hardware expenditure at the same time, and generating a large number of challenge response pairs through dual-edge sampling realized by the two arbiters.


Find Patent Forward Citations

Loading…