The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 04, 2025

Filed:

Jan. 09, 2024
Applicant:

Drut Technologies Inc., Nashua, NH (US);

Inventors:

Jitender Miglani, Hollis, NH (US);

Will Ferry, Bloomsburg, PA (US);

Dileep Desai, San Jose, CA (US);

Assignee:

Drut Technologies Inc., Nashua, NH (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/42 (2006.01); G02B 6/35 (2006.01); G06F 13/40 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4027 (2013.01); G02B 6/3518 (2013.01); G02B 6/3546 (2013.01); G06F 13/4282 (2013.01);
Abstract

Described are methods for configuring computing system for and computing systems for PCIe communication between remote computing assets. The system uses a fabric interface device configured to receive multi-lane serial PCIe data from functional elements of a computing asset through a multi-lane PCIe bus, and to transparently extend the multi-lane PCIe bus by converting the multi-lane PCIe data into a retimed parallel version of the PCIe multi-lane data to be sent on bidirectional data communication paths. The fabric interface device is also configured so that the multi-lane PCIe bus can have a first number of lanes and the bidirectional data communication paths can have a different second number of lanes.


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