The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 04, 2025

Filed:

Aug. 28, 2023
Applicant:

Mellanox Technologies, Ltd., Yokneam, IL;

Inventors:

Yaniv Strassberg, Yokneam, IL;

Guy Harel, Haifa, IL;

Gabi Liron, Yokneam Illit, IL;

Yuval Itkin, Zoran, IL;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 12/0815 (2016.01); G06F 12/084 (2016.01); G06F 12/14 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0815 (2013.01); G06F 12/084 (2013.01); G06F 12/1408 (2013.01);
Abstract

A peripheral device includes a processor, a memory interface, a host interface and a cache controller. The processor executes software code. The cache memory caches a portion of the software code. The memory interface communicates with a NVM storing a replica of the software code. The host interface communicates with hosts storing additional replicas of the software code. The cache controller is to determine whether each host is allocated for code fetching, to receive a request from the processor for a segment of the software code, when available in the cache memory to fetch the segment from the cache memory, when unavailable in the cache memory and at least one host is allocated, to fetch the segment from the hosts that are allocated, when unavailable in the cache memory and no host is allocated, to fetch the segment from the NVM, and to serve the fetched segment to the processor.


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