Storage system and method for hiding error checking and correcting (ecc) encoding delay

Abstract

A storage system and method for hiding Error Checking and Correcting (ECC) encoding delay are disclosed. An output of a data register is configured to be two data streams. One data stream transmits an input write data and an ECC check code to the SRAM through an ECC encoding module and an intermediate write data register, and the other data stream inputs the input write data to a read data selector through a bypass register module through the intermediate write data register and the bypass register module. The other input of the read data selector is the data set whose errors have been checked and corrected by the ECC encoding error checking module which reads the data set from the SRAM. The read data selector is configured to transmit the selected input data to the read data register. According to the present disclosure, when data at the address is read right after the data is written to the address, the read data selector selects to output the write data received from the bypass register module; but when data is written to an address but data at an other address is read, the read data selector selects to output the data set whose errors have been checked and corrected by the ECC encoding error checking module which reads the data set from the SRAM.