The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 28, 2025
Filed:
May. 31, 2021
Chengdu Boe Optoelectronics Technology Co., Ltd., Sichuan, CN;
Boe Technology Group Co., Ltd., Beijing, CN;
Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan, CN;
BOE Technology Group Co., Ltd., Beijing, CN;
Abstract
A display substrate () and a display device, which can reduce the number of power lines (), and improve the light transmittance of a first display sub-region (). The display substrate () includes a first display sub-region () and a second display sub-region (), where a light transmittance of the first display sub-region () is higher than that of the second display sub-region (); the display substrate () includes: a plurality of first-type sub-pixels () and a plurality of power lines (), where the first-type sub-pixels () and the power lines () are located in the first display sub-region (); the first-type sub-pixels () are arranged in an array along a row direction (X) and a column direction (Y); each first-type sub-pixel () comprises a light emitting element and a pixel circuit for driving the light emitting element to emit light; the plurality of power lines () are connected to one another; the plurality of power lines () comprise at least one of first-type power lines () or second-type power lines (), the first-type power lines () are configured to be connected to pixel circuits of the first-type sub-pixels () arranged along the row direction (X), and the second-type power lines () are configured to be connected to pixel circuits of the first-type sub-pixels () arranged in the column direction (Y); a sum of a number of the first-type power lines () and a number of the second-type power lines () is smaller than a sum of a number of rows and a number of columns of the array.