The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 28, 2025

Filed:

Apr. 14, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Suhwan Lim, Hanam-si, KR;

Nambin Kim, Seoul, KR;

Samki Kim, Hwaseong-si, KR;

Taehun Kim, Gwacheon-si, KR;

Hanvit Yang, Suwon-si, KR;

Changhee Lee, Hwaseong-si, KR;

Jaehun Jung, Seongnam-si, KR;

Hyeongwon Choi, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 43/27 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 41/40 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 41/40 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02);
Abstract

A semiconductor device includes a lower structure including a semiconductor substrate and circuit devices on the semiconductor substrate; a stack structure including interlayer insulating layers and gate electrodes alternating in a vertical direction; and a channel structure penetrating the stack structure. The channel structure includes a core insulating layer, a channel layer, a gate dielectric layer, and a channel pad. A portion of the channel pad overlaps an uppermost gate electrode among the gate electrodes in a horizontal direction. The channel pad includes a first pad layer and a second pad layer on the first pad layer. The second pad layer includes doped polysilicon that is doped with impurities and having N-type conductivity. The first pad layer includes at least one of an undoped polysilicon region and a doped polysilicon region having N-type conductivity and having an impurity concentration lower than an impurity concentration of the second pad layer.


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