The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 28, 2025

Filed:

Feb. 03, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Junghwa Kim, Seoul, KR;

Junso Pak, Seongnam-si, KR;

Heeseok Lee, Suwon-si, KR;

Moonseob Jeong, Seongnam-si, KR;

Jisoo Hwang, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 23/538 (2006.01); H05K 1/02 (2006.01); H05K 1/18 (2006.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
H05K 1/181 (2013.01); H01L 23/481 (2013.01); H01L 23/49816 (2013.01); H01L 23/5386 (2013.01); H01L 24/14 (2013.01); H01L 24/16 (2013.01); H01L 24/17 (2013.01); H05K 1/0228 (2013.01); H01L 25/0655 (2013.01); H01L 2224/14135 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/1712 (2013.01); H01L 2924/1205 (2013.01); H01L 2924/15311 (2013.01); H05K 2201/10734 (2013.01);
Abstract

A semiconductor package including a circuit board including a first wiring region, a die mounting region surrounding the first wiring region, and a second wiring region surrounding the die mounting region; a plurality of wiring balls on the first wiring region and the second wiring region and spaced apart from one another, the plurality of wiring balls including a plurality of first wiring balls on the first wiring region and a plurality of second wiring balls on the second wiring region; a die on the die mounting region, the die including a plurality of unit chips spaced apart from one another, and a die-through region corresponding to the first wiring region and exposing the first wiring balls; and a plurality of die balls on the die and the die mounting region, the plurality of die balls being spaced apart from one another and electrically coupled to the circuit board.


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