Reset synchronizing circuit and glitchless clock buffer circuit for preventing start-up failure, and iq divider circuit

Abstract

A clock frequency divider circuit and a receiver are provided. The clock frequency divider circuit includes a reset retimer circuit configured to receive a reset signal and a clock signal, output a reset buffer signal of a differential signal pair obtained by buffering the reset signal, and output a reset synchronization signal obtained by synchronizing the reset signal with the clock signal, a clock buffer circuit configured to receive the clock signal and the reset synchronization signal and output a clock buffer signal of a differential signal pair obtained by buffering the clock signal, and an IQ divider circuit configured to output first through fourth output signals having different phases based on the reset buffer signal and the clock buffer signal.