The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 28, 2025

Filed:

Oct. 06, 2020
Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventors:

David Lim, Cupertino, CA (US);

Hsien-Li Lin, Taipei, TW;

Tom Jozef Denis Verbeure, Sunnyvale, CA (US);

Gerrit Slavenburg, Hayward, CA (US);

Seth Schneider, San Jose, CA (US);

Assignee:

NVIDIA Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 43/08 (2022.01); G06F 3/14 (2006.01); H04L 43/065 (2022.01); H04L 43/0852 (2022.01); H04L 43/106 (2022.01);
U.S. Cl.
CPC ...
H04L 43/0858 (2013.01); G06F 3/14 (2013.01); H04L 43/065 (2013.01); H04L 43/0852 (2013.01); H04L 43/106 (2013.01);
Abstract

In various examples, latency of human interface devices (HIDs) may be accounted for in determining an end-to-end latency of a system. For example, when an input is received at an HID, an amount of time for the input to reach a connected device may be computed by the HID and included in a data packet transmitted by the HID device to the connected device. The addition of the peripheral latency to the end-to-end latency determination may provide a more comprehensive latency result for the system and, where the peripheral latency of an HID is determined to have a non-negligible contribution to the end-to-end latency, a new HID component may be implemented, a configuration setting associated with the HID component may be updated, and/or other actions may be taken to reduce the contribution of the peripheral latency to the overall latency of the system.


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