The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 28, 2025

Filed:

Mar. 21, 2022
Applicant:

Avago Technologies International Sales Pte. Limited, Singapore, SG;

Inventors:

Ullas Singh, Irvine, CA (US);

Namik Kocaman, Irvine, CA (US);

Mohammadamin Torabi, Mission Viejo, CA (US);

Meisam Honarvar Nazari, Irvine, CA (US);

Mehmet Batuhan Dayanik, Irvine, CA (US);

Delong Cui, Irvine, CA (US);

Jun Cao, Irvine, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/06 (2006.01); H03M 1/46 (2006.01);
U.S. Cl.
CPC ...
H03M 1/462 (2013.01); H03M 1/0697 (2013.01); H03M 1/468 (2013.01);
Abstract

Systems and methods are related to a successive approximation analog to digital converter (SAR ADC). In one aspect, a method includes sampling, by a sample and digital to analog conversion (DAC) circuit, an input voltage to obtain a sampled voltage. The method also includes determining, by a comparator coupled to a set of storage circuits, a state of a plurality of bits corresponding to the sampled voltage. The comparator has a current parameter or voltage parameter adjusted based upon a conversion margin. Adjustment of the current parameter or the voltage parameter affects speed of determining the state of the bits. The method also includes storing the bits in the set of storage circuits. In some aspects, an SAR ADC is configured to perform the method.


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