The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 28, 2025

Filed:

Jul. 30, 2021
Applicant:

Cobham Advanced Electronic Solutions Inc., Lansdale, PA (US);

Inventor:

Chul Hong Park, Blue Bell, PA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 23/00 (2006.01); H01L 23/367 (2006.01); H01L 23/373 (2006.01); H01R 13/03 (2006.01); H01R 13/05 (2006.01); H01R 13/42 (2006.01); H01R 13/646 (2011.01); H05K 7/20 (2006.01); H01R 12/71 (2011.01); H01R 13/11 (2006.01); H01R 107/00 (2006.01);
U.S. Cl.
CPC ...
H01R 13/03 (2013.01); H01L 23/3677 (2013.01); H01L 23/3736 (2013.01); H01L 23/49513 (2013.01); H01L 23/49568 (2013.01); H01L 24/17 (2013.01); H01R 13/055 (2013.01); H01R 13/42 (2013.01); H01R 13/646 (2013.01); H05K 7/20145 (2013.01); H05K 7/20154 (2013.01); H01R 12/716 (2013.01); H01R 13/11 (2013.01); H01R 2107/00 (2013.01); H05K 7/20136 (2013.01);
Abstract

The semiconductor chip includes a semiconductor substrate having a surface, a circuit formed on the surface, and a plurality of pillars coupled to the surface adjacent to the circuit. The plurality of pillars is thermally conductive and is thermally coupled to the circuit so as to dissipate heat generated by the circuit. The semiconductor substrate, circuit, and plurality of pillars are integral parts of the integrated semiconductor chip. A method of fabricating the integrated semiconductor chip includes providing a semiconductor substrate having a surface. The method includes forming a circuit on the surface, and forming a plurality of pillars thermally coupled to the surface adjacent to the circuit.


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