The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 28, 2025

Filed:

Dec. 21, 2023
Applicant:

Rohm Co., Ltd., Kyoto, JP;

Inventor:

Hirotaka Otake, Kyoto, JP;

Assignee:

ROHM CO., LTD., Kyoto, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/085 (2006.01); H01L 21/76 (2006.01); H01L 21/8252 (2006.01); H01L 29/06 (2006.01); H01L 29/20 (2006.01); H01L 29/205 (2006.01); H01L 29/66 (2006.01); H01L 29/778 (2006.01);
U.S. Cl.
CPC ...
H01L 27/085 (2013.01); H01L 21/7605 (2013.01); H01L 21/8252 (2013.01); H01L 29/0653 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/66462 (2013.01); H01L 29/7786 (2013.01); H01L 29/7787 (2013.01);
Abstract

The present invention provides a nitride semiconductor device, including: a silicon substrate; a first lateral transistor over a first region of the silicon substrate and including: a first nitride semiconductor layer formed over the silicon substrate; and a first gate electrode, a first source electrode and a first drain electrode formed over the first nitride semiconductor layer; a second lateral transistor over a second region of the silicon substrate and including: a second nitride semiconductor layer formed over the silicon substrate; and a second gate electrode, a second source electrode and a second drain electrode formed over the second nitride semiconductor layer; a first separation trench formed over a third region; a source/substrate connecting via hole formed over the third region; a first interlayer insulating layer formed over the first source electrode and the second source electrode; and a second interlayer insulating layer formed in the first separation trench.


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