The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 28, 2025
Filed:
Apr. 12, 2022
Stmicroelectronics S.r.l., Agrate Brianza, IT;
Alma Mater Studiorum—universita' Di Bologna, Bologna, IT;
Marco Pasotti, Travaco' Siccomario, IT;
Marcella Carissimi, Bergamo, IT;
Alessio Antolini, Bologna, IT;
Eleonora Franchi Scarselli, Bologna, IT;
Antonio Gnudi, Bologna, IT;
Andrea Lico, Polia, IT;
STMicroelectronics S.r.l., Agrate Brianza, IT;
Abstract
An in-memory computation (IMC) circuit includes a memory array formed by memory cells arranged in row-by-column matrix. Computational weights for an IMC operation are stored in the memory cells. Each column includes a bit line connected to the memory cells. A switching circuit is connected between each bit line and a corresponding column output. The switching circuit is controlled to turn on to generate the analog signal dependent on the computational weight and for a time duration controlled by the coefficient data signal. A column combining circuit combines (by addition and/or subtraction) and integrates analog signals at the column outputs of the biasing circuits. The addition/subtraction is dependent on one or more a sign of the coefficient data and a sign of the computational weight and may further implement a binary weighting function.