The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 28, 2025

Filed:

Jun. 29, 2023
Applicant:

Lightelligence Pte. Ltd., Singapore, SG;

Inventors:

Huaiyu Meng, Medford, MA (US);

Yichen Shen, Hangzhou, CN;

Yelong Xu, Allston, MA (US);

Gilbert Hendry, Swampscott, MA (US);

Longwu Ou, Cambridge, MA (US);

Jingdong Deng, Acton, MA (US);

Ronald Gagnon, North Grafton, MA (US);

Cheng-Kuan Lu, Littleton, MA (US);

Maurice Steinman, Marlborough, MA (US);

Mike Evans, Arlington, MA (US);

Jianhua Wu, Quincy, MA (US);

Assignee:

Lightelligence PTE. Ltd., Singapore, SG;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06N 3/067 (2006.01); G06E 1/04 (2006.01);
U.S. Cl.
CPC ...
G06N 3/0675 (2013.01); G06E 1/045 (2013.01);
Abstract

An optoelectronic computing system includes a first semiconductor die having a photonic integrated circuit (PIC) and a second semiconductor die having an electronic integrated circuit (EIC). The PIC includes optical waveguides, in which input values are encoded on respective optical signals carried by the optical waveguides. The PIC includes an optical copying distribution network having optical splitters. The PIC includes an array of optoelectronic circuitry sections, each receiving an optical wave from one of the output ports of the optical copying distribution network, and each optoelectronic circuitry section includes: at least one photodetector detecting at least one optical wave from the optoelectronic operation. The EIC includes electrical input ports receiving respective electrical values. The first semiconductor die and the second semiconductor die are electrically coupled in a controlled collapse chip connection, with the electrical output port of the PIC connected to one of the electrical input ports of the EIC.


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