The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 28, 2025

Filed:

Mar. 18, 2021
Applicant:

Korea Institute of Science and Technology, Seoul, KR;

Inventors:

Joon Young Kwak, Seoul, KR;

Suyoun Lee, Seoul, KR;

Inho Kim, Seoul, KR;

Jong-Keuk Park, Seoul, KR;

Kyeong Seok Lee, Seoul, KR;

Jaewook Kim, Seoul, KR;

Jongkil Park, Seoul, KR;

YeonJoo Jeong, Seoul, KR;

Gyuweon Hwang, Seoul, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06N 3/063 (2023.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); H01L 29/792 (2006.01);
U.S. Cl.
CPC ...
G06N 3/063 (2013.01); G11C 16/0466 (2013.01); G11C 16/10 (2013.01); H01L 29/792 (2013.01);
Abstract

Embodiments of inventive concepts relate to a neuromorphic circuit including a flash memory-based spike regulator capable of generating a stable spike signal with a small number of devices. The neuromorphic circuit may generate a simple and stable spike signal using a flash memory-based spike regulator. Therefore, it is possible to implement a semiconductor neuromorphic circuit at low power and low cost by using the spike regulator of the present invention. Example embodiments of inventive concepts provide a neuromorphic circuit comprising a control signal generator for generating a control signal for generating a pulse signal; and a spike regulator for generating a spike signal in response to the control signal. Wherein the spike regulator comprises a first transistor for switching an input signal transmitted to one terminal to the other terminal in response to the control signal; and a first flash memory type transistor having a drain terminal connected to the other terminal of the first transistor and transferring the switched input signal to a source terminal as a spike signal.


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