The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 28, 2025

Filed:

Jan. 19, 2023
Applicant:

Sambanova Systems, Inc., Palo Alto, CA (US);

Inventors:

Arnav Goel, Palo Alto, CA (US);

Neal Sanghvi, Palo Alto, CA (US);

Jiayu Bai, Palo Alto, CA (US);

Qi Zheng, Palo Alto, CA (US);

Ravinder Kumar, Palo Alto, CA (US);

Assignee:

SambaNova Systems, Inc., Palo Alto, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01); G06F 12/02 (2006.01); G06F 13/16 (2006.01); G06F 13/28 (2006.01);
U.S. Cl.
CPC ...
G06F 13/28 (2013.01); G06F 12/0238 (2013.01); G06F 13/1642 (2013.01);
Abstract

A heterogeneous processing system including a host processor, a first processor with a first memory and a first data transfer resource, a second processor with a second memory, and switch and bus circuitry that communicatively couples the processors and the data transfer resource. The host processor is programmed to map virtual addresses of the second memory to physical addresses of the switch and bus circuitry and to configure the first processor to perform one memory to memory transfer operation between the first and second memories using the data transfer resource. The first processor may be configured to program the first data transfer resource. A method including mapping virtual addresses of the second memory to physical addresses of the switch and bus circuitry, and configuring the first processor to perform one memory to memory transfer operation between the first and second memories using the first data transfer resource.


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