The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 21, 2025

Filed:

Aug. 31, 2022
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Tomoki Chiba, Fujisawa Kanagawa, JP;

Daisaburo Takashima, Yokohama Kanagawa, JP;

Hidehiro Shiga, Yokohama Kanagawa, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 63/00 (2023.01); G11C 11/16 (2006.01); G11C 13/00 (2006.01); H10B 61/00 (2023.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01);
U.S. Cl.
CPC ...
H10B 63/34 (2023.02); G11C 11/1673 (2013.01); G11C 13/0026 (2013.01); G11C 13/004 (2013.01); H10B 61/22 (2023.02); H10B 63/845 (2023.02); H10N 70/231 (2023.02); H10N 70/8413 (2023.02); H10N 70/8825 (2023.02); H10N 70/8828 (2023.02); H10N 70/8833 (2023.02); G11C 2213/71 (2013.01);
Abstract

A variable resistance non-volatile memory includes a semiconductor substrate, a first electrode line extending in a first direction away from the semiconductor substrate, a second electrode line extending in the first direction parallel to the first electrode line, an insulating film between the first and second electrode lines, a variable resistance film formed on the first electrode line, a low electrical resistance layer formed on the variable resistance film and having a lower electrical resistance than the variable resistance film, a semiconductor film in contact with the low electrical resistance layer and the insulating film, and formed on opposite surfaces of the second electrode line, a gate insulator film extending in the first direction and in contact with the semiconductor film, and a voltage application electrode that extends in a second direction that crosses the first direction, and is in contact with the gate insulator film.


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