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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12207460 B1

PDFFull Text
Date of Patent:
Jan. 21, 2025

Filed:

May. 29, 2020

Method of manufacturing semiconductor device having a subtrate with a protruding portion having different heights in regions overlapped with different gate electrodes

Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventor:

Tomohiro Yamashita, Tokyo, JP;

Assignee:

RENESAS ELECTRONICS CORPORATION, Tokyo, JP;

Attorney:

Rimon P.C.

Primary Examiner:

Joshua Benitez Rosario

Assistant Examiner:

Scott E Bauman

Int. Cl.
CPC ...
H10B 41/30 (2023.01); H01L 21/28 (2006.01); H01L 21/8234 (2006.01); H01L 27/12 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/792 (2006.01); H10B 43/30 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01);
U.S. Cl.
CPC ...
H10B 41/30 (2023.02); H01L 21/823431 (2013.01); H01L 27/1211 (2013.01); H01L 29/40117 (2019.08); H01L 29/41791 (2013.01); H01L 29/42344 (2013.01); H01L 29/42376 (2013.01); H01L 29/66795 (2013.01); H01L 29/66818 (2013.01); H01L 29/66833 (2013.01); H01L 29/7855 (2013.01); H01L 29/792 (2013.01); H10B 43/30 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02);
Abstract

A semiconductor device includes: a fin that is a portion of a semiconductor substrate, protrudes from a main surface of the semiconductor substrate, has a width in a first direction, and extends in a second direction; a control gate electrode that is arranged on the fin via a first gate insulating film and extends in the first direction; and a memory gate electrode that is arranged on the fin via a second gate insulating film and extends in the first direction. Further, a width of the fin in a region in which the memory gate electrode is arranged via the second gate insulating film having a film thickness larger than the first gate insulating film is smaller than a width of the fin in a region in which the control gate electrode is arranged via the first gate insulating film.

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