The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 21, 2025
Filed:
Feb. 21, 2024
Applicant:
Sambanova Systems, Inc., Palo Alto, CA (US);
Inventors:
Fahim ur Rahman, Palo Alto, CA (US);
Jinuk Shin, San Jose, CA (US);
Assignee:
SambaNova Systems, Inc., Palo Alto, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/10 (2006.01); H03H 17/02 (2006.01); H03L 7/081 (2006.01); H03L 7/093 (2006.01); H03H 17/00 (2006.01);
U.S. Cl.
CPC ...
H03L 7/10 (2013.01); H03H 17/02 (2013.01); H03L 7/0812 (2013.01); H03L 7/093 (2013.01); H03H 2017/0081 (2013.01);
Abstract
An integrated circuit (IC) features a delay-locked loop (DLL) with a DLL signal input. The DLL comprises a delay line with multiple delay stages, a gater with clock input, and a phase-frequency detector (PFD). The delay line's signal input is linked to the DLL signal input, while the gater's inputs are connected to phase outputs of the delay line. The gater's clock input is tied to the DLL signal input, and its outputs feed into the PFD inputs. The PFD generates outputs that are used by a loop filter to control the speed of the delay line.