The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 21, 2025
Filed:
Jul. 18, 2023
Electronics and Telecommunications Research Institute, Daejeon, KR;
Yi-Gyeong Kim, Daejeon, KR;
Young-Su Kwon, Daejeon, KR;
Su-Jin Park, Daejeon, KR;
Young-Deuk Jeon, Sejong-si, KR;
Min-Hyung Cho, Daejeon, KR;
Jae-Woong Choi, Daejeon, KR;
ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE, Daejeon, KR;
Abstract
Disclosed herein are a duty cycle monitoring method and apparatus for a memory interface, including receiving a clock signal as input and generating a first delay time offset and a second delay time offset, receiving the clock signal and the first delay time offset and then outputting a first delayed signal, receiving the first delayed signal and the second delay time offset and then outputting a second delayed signal, receiving the clock signal and the second delayed signal and then outputting a delay value corresponding to a half-period of the clock signal, and monitoring, based on the first delayed signal, whether a duty cycle of the clock signal conforms to a duty cycle specification.