The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 21, 2025

Filed:

Nov. 18, 2021
Applicant:

Sumitomo Electric Industries, Ltd., Osaka, JP;

Inventors:

Yuki Ito, Osaka, JP;

Mitsuru Ekawa, Osaka, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 33/48 (2010.01); H01L 33/58 (2010.01); H01L 33/62 (2010.01);
U.S. Cl.
CPC ...
H01L 33/483 (2013.01); H01L 33/58 (2013.01); H01L 33/62 (2013.01);
Abstract

A semiconductor optical device, in which a light emitting region and a modulator region are integrated, includes a first mesa disposed in the light emitting region, protruding in a direction that intersects a light propagation direction, and including an active layer, first and second buried layers disposed on the first mesa in a direction that intersects the light propagation direction and sequentially stacked in a direction in which the first mesa protrudes, a first semiconductor layer disposed on the first mesa and the second buried layer, a second mesa disposed in the modulator region and including a light absorption layer, and a third buried layer disposed on the second mesa. The first semiconductor layer and the first buried layer each have a first conductivity type. The second buried layer has a second conductivity type different from the first conductivity type, and the third buried layer is a semi-insulating semiconductor layer.


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