The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 21, 2025
Filed:
Aug. 18, 2020
Csmc Technologies Fab2 Co., Ltd., Wuxi New District, CN;
Huajun Jin, Wuxi New District, CN;
Guipeng Sun, Wuxi New District, CN;
CSMC TECHNOLOGIES FAB2 CO., LTD., Wuxi New District, CN;
Abstract
The present invention relates to an LDMOS device and a method of forming the device, in which a barrier layer includes n etch stop layers. Insulating layers are formed between adjacent etch stop layers. Since an interlayer dielectric layer and the insulating layers are both oxides that differ from the material of the etch stop layers, etching processes can be stopped at the n etch stop layers when they are proceeding in the oxides, thus forming n field plate holes terminating at the respective n etch stop layers. A lower end of the first field plate hole proximal to a gate structure is closest to a drift region, and a lower end of the n-th field plate hole proximal to a drain region is farthest from the drift region. With this arrangement, more uniform electric field strength can be obtained around front and rear ends of the drift region, resulting in an effectively improved electric field distribution throughout the drift region and thus in an increased breakdown voltage.