The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 21, 2025
Filed:
Dec. 14, 2023
Applicant:
Socionext Inc., Kanagawa, JP;
Inventors:
Toshio Hino, Yokohama, JP;
Junji Iwahori, Yokohama, JP;
Assignee:
SOCIONEXT INC., Kanagawa, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/82 (2006.01); B82Y 10/00 (2011.01); H01L 21/8238 (2006.01); H01L 27/02 (2006.01); H01L 27/092 (2006.01); H01L 27/118 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01); H01L 29/775 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11807 (2013.01); B82Y 10/00 (2013.01); H01L 21/823821 (2013.01); H01L 21/823828 (2013.01); H01L 27/0207 (2013.01); H01L 27/0924 (2013.01); H01L 29/0673 (2013.01); H01L 29/0696 (2013.01); H01L 29/0847 (2013.01); H01L 29/1079 (2013.01); H01L 29/4238 (2013.01); H01L 29/42392 (2013.01); H01L 29/775 (2013.01); H01L 29/78696 (2013.01); H01L 2027/11864 (2013.01); H01L 2027/11874 (2013.01);
Abstract
A semiconductor integrated circuit device including standard cells including fin transistors includes, at a cell row end, a cell-row-terminating cell that does not contribute to a logical function of a circuit block. The cell-row-terminating cell includes a plurality of fins extending in an X direction. Ends of the plurality of fins on the inner side of the circuit block are near a gate structure placed at a cell end and do not overlap with the gate structure in a plan view, and ends of the plurality of fins on an outer side of the circuit block overlap with any one of a gate structure in a plan view.