The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 21, 2025

Filed:

Jul. 29, 2024
Applicant:

Diodes Incorporated, Plano, TX (US);

Inventor:

Shiau-Shi Lin, Taoyuan, TW;

Assignee:

Diodes Incorporated, Plano, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/10 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/495 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/105 (2013.01); H01L 23/3107 (2013.01); H01L 23/49517 (2013.01); H01L 23/49537 (2013.01); H01L 24/19 (2013.01); H01L 24/24 (2013.01); H01L 25/50 (2013.01); H01L 24/16 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/19 (2013.01); H01L 2224/24146 (2013.01); H01L 2225/1041 (2013.01);
Abstract

The present invention relates to an electronic component package and a manufacturing method therefor. In an embodiment, the electronic component package comprises: a first metal layer, a high-voltage transistor semiconductor die, a first molding compound layer, a second metal layer, a first vertical connection structure, a second vertical connection structure, a control circuit bare chip, and a second molding compound layer. In the electronic component package of the present invention, a lead frame and electrical leads are replaced with the metal layers and the vertical connection structures, so that the position of the electrical connection of the chip is more flexible and the heat dissipation effect is better. Compared with the lead frames and the electrical leads, the electronic component package of the present disclosure is more suitable for packaging high-voltage or high-current chips.


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