The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 21, 2025
Filed:
May. 26, 2023
Applicant:
Texas Instruments Incorporated, Dallas, TX (US);
Inventors:
Rafael Jose Lizares Guevara, Metro Manila, PH;
Jovenic Romero Esquejo, Baguio, PH;
Arvin Cedric Quiambao Mallari, San Fernando, PH;
Assignee:
TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/4952 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 24/81 (2013.01); H01L 2224/11552 (2013.01); H01L 2224/13011 (2013.01); H01L 2224/13564 (2013.01); H01L 2224/81815 (2013.01);
Abstract
In some examples, a quad flat no lead (QFN) semiconductor package comprises a flip chip semiconductor die having a surface and circuitry formed in the surface; and a conductive pillar coupled to the semiconductor die surface. The conductive pillar has a distal end relative to the semiconductor die, the distal end having a cavity including a cavity floor and one or more cavity walls circumscribing the cavity floor. The one or more cavity walls are configured to contain solder.