The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 21, 2025

Filed:

Jan. 05, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Sung-Rae Kim, Seoul, KR;

Myung Kyu Lee, Seoul, KR;

Ki Jun Lee, Seoul, KR;

Jun Jin Kong, Yongin-si, KR;

Yeong Geol Song, Seoul, KR;

Jin-Hoon Jang, Uiwang-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/42 (2006.01); G11C 29/00 (2006.01); G11C 29/14 (2006.01); G11C 29/18 (2006.01); G11C 29/44 (2006.01);
U.S. Cl.
CPC ...
G11C 29/42 (2013.01); G11C 29/14 (2013.01); G11C 29/18 (2013.01); G11C 29/4401 (2013.01); G11C 29/783 (2013.01);
Abstract

A memory device includes a memory cell array including memory cells arranged in a plurality of rows; an ECC engine configured to detect an error in first data that is read from the memory cell array in response to a read command and a read address, to output a first error occurrence signal, and to correct the error in the first data; a row fail detector configured to output a fail row address, which indicates a fail row among the plurality of rows; and a flag generator configured to receive the read address, the first error occurrence signal, and the fail row address, and to generate a decoding state flag, which indicates whether an error is detected and whether an error is corrected, and a fail row flag, which indicates that a read row address included in the read address is the fail row address.


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