The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 21, 2025

Filed:

Jul. 30, 2021
Applicants:

Chengdu Boe Optoelectronics Technology Co., Ltd., Sichuan, CN;

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Yao Huang, Beijing, CN;

Benlian Wang, Beijing, CN;

Ming Hu, Beijing, CN;

Lang Liu, Beijing, CN;

Kai Zhang, Beijing, CN;

Weiyun Huang, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/3233 (2016.01); G09G 3/20 (2006.01); H10K 59/121 (2023.01);
U.S. Cl.
CPC ...
G09G 3/3233 (2013.01); G09G 3/2007 (2013.01); H10K 59/1213 (2023.02); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2300/0852 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0247 (2013.01); G09G 2320/0257 (2013.01); G09G 2330/021 (2013.01);
Abstract

A pixel driving circuit includes: a driving transistor, a data write circuit, a threshold compensation circuit, a first capacitor, and a second capacitor. A gate of the driving transistor is coupled to a first node, a first electrode is coupled to a second node, and a second electrode is coupled to a third node. The data write circuit is configured to transmit a signal of a data signal terminal to the second node in response to a signal of a first gate driving signal terminal. The threshold compensation circuit is configured to communicate the first node with the third node in response to a signal of a second gate driving signal terminal. The first capacitor is coupled between the first node and the first gate driving signal terminal. The second capacitor is coupled between the first node and the second gate driving signal terminal.


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