The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 21, 2025

Filed:

Mar. 18, 2021
Applicant:

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Jiangnan Lu, Beijing, CN;

Guangliang Shang, Beijing, CN;

Xinshe Yin, Beijing, CN;

Libin Liu, Beijing, CN;

Jianchao Zhu, Beijing, CN;

Hao Zhang, Beijing, CN;

Ke Feng, Beijing, CN;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G09G 3/3233 (2016.01); G09G 3/3258 (2016.01); G09G 3/3266 (2016.01); G09G 3/36 (2006.01); G11C 19/28 (2006.01);
U.S. Cl.
CPC ...
G09G 3/3233 (2013.01); G09G 3/3258 (2013.01); G09G 3/3266 (2013.01); G09G 3/36 (2013.01); G11C 19/28 (2013.01); G09G 2230/00 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/0224 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/061 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0295 (2013.01); G09G 2320/045 (2013.01);
Abstract

A shift register unit, a driving method thereof, a gate driving circuit and a display panel are provided. The shift register unit includes an input circuit, a reset circuit, a first output circuit and a second output circuit; the input circuit is configured to control a level of a first node in response to a first input signal; the reset circuit is configured to reset the first node in response to a reset signal; the first output circuit is configured to output a shift signal under control of the level of the first node; and the second output circuit is configured to, in a first phase, under control of the level of the first node, output a plurality of sub-pulses at the first output terminal as a first output signal in a case where the shift output terminal outputs a first level of the shift signal.


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