The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 21, 2025

Filed:

Nov. 30, 2022
Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventors:

Harold Carter Edwards, Campbell, CA (US);

Kyrylo Perelygin, Broomfield, CO (US);

Maciej Tyrlik, Durham, NC (US);

Gokul Ramaswamy Hirisave Chandra Shekhara, Bangalore, IN;

Balaji Krishna Yugandhar Atukuri, San Jose, CA (US);

Rishkul Kulkarni, Austin, TX (US);

Konstantinos Kyriakopoulos, Weinsberg, DE;

Edward H. Gornish, Palo Alto, CA (US);

David Allan Berson, Portland, OR (US);

Bageshri Sathe, Pune, IN;

James Player, Campbell, CA (US);

Aman Arora, Bengaluru, IN;

Alan Kaatz, Seattle, WA (US);

Andrew Kerr, Atlanta, GA (US);

Haicheng Wu, Cary, NC (US);

Cris Cecka, San Jose, CA (US);

Vijay Thakkar, Boston, MA (US);

Sean Treichler, Piedmont, CA (US);

Jack H. Choquette, Palo Alto, CA (US);

Aditya Avinash Atluri, Redmond, WA (US);

Apoorv Parle, San Jose, CA (US);

Ronny Meir Krashinsky, Portola Valley, CA (US);

Cody Addison, Cedar Park, TX (US);

Girish Bhaskarrao Bharambe, Pune, IN;

Assignee:

NVIDIA CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 17/16 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3001 (2013.01); G06F 9/30087 (2013.01); G06F 9/3009 (2013.01); G06F 9/3834 (2013.01); G06F 17/16 (2013.01);
Abstract

Apparatuses, systems, and techniques to perform computational operations in response to one or more compute uniform device architecture (CUDA) programs. In at least one embodiment, one or more computational operations are to cause one or more other computational operations to wait until a portion of matrix multiply-accumulate (MMA) operations have been performed.


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