The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 21, 2025

Filed:

Dec. 03, 2021
Applicant:

University of Florida Research Foundation, Incorporated, Gainesville, FL (US);

Inventors:

Mark M. Tehranipoor, Gainesville, FL (US);

Farimah Farahmandi, Gainesville, FL (US);

Huanyu Wang, Gainesville, FL (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 21/72 (2013.01); G06F 21/55 (2013.01); G06F 21/57 (2013.01); G06F 21/75 (2013.01); G06F 30/337 (2020.01); G06F 30/398 (2020.01);
U.S. Cl.
CPC ...
G06F 21/75 (2013.01); G06F 21/554 (2013.01); G06F 21/577 (2013.01); G06F 30/398 (2020.01);
Abstract

Various embodiments provide methods, systems, computer program products, apparatuses, and/or the like for assessing vulnerability of an IC design to fault injection attacks, such as through a security property-driven vulnerability assessment framework for efficiently evaluating faults with respect to certain security properties associated with the IC design. In one embodiment, a method is provided. The method includes generating, using a fault-injection technique specification, one or more fault models describing attributes of one or more faults. The method further includes selecting, using the fault models and executable security properties associated with a design file of an IC design, a fault list identifying a plurality of possible faults for the IC design. The method further includes identifying, based at least in part on performing a fault simulation on the design file with the fault list, critical locations of the IC design. The method further includes implementing protections at the critical locations.


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