The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 21, 2025

Filed:

Sep. 07, 2023
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Niraj Nandan, Plano, TX (US);

Hetul Sanghvi, Murphy, TX (US);

Mihir Mody, Bangalore, IN;

Gary Cooper, Oakmont, PA (US);

Anthony Lell, San Antonio, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 9/48 (2006.01); G06F 11/22 (2006.01); G06F 11/273 (2006.01); G06F 13/16 (2006.01); G06F 13/28 (2006.01);
U.S. Cl.
CPC ...
G06F 11/2733 (2013.01); G06F 9/4843 (2013.01); G06F 11/2242 (2013.01); G06F 13/1668 (2013.01); G06F 13/28 (2013.01);
Abstract

A system to implement debugging for a multi-threaded processor is provided. The system includes a hardware thread scheduler configured to schedule processing of data, and a plurality of schedulers, each configured to schedule a given pipeline for processing instructions. The system further includes a debug control configured to control at least one of the plurality of schedulers to halt, step, or resume the given pipeline of the at least one of the plurality of schedulers for the data to enable debugging thereof. The system further includes a plurality of hardware accelerators configured to implement a series of tasks in accordance with a schedule provided by a respective scheduler in accordance with a command from the debug control. Each of the plurality of hardware accelerators is coupled to at least one of the plurality of schedulers to execute the instructions for the given pipeline and to a shared memory.


Find Patent Forward Citations

Loading…