The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 21, 2025
Filed:
May. 09, 2023
Applicant:
SK Hynix Inc., Icheon-si, KR;
Inventors:
Ji Hyo Kang, Icheon-si, KR;
Kyung Hoon Kim, Icheon-si, KR;
Assignee:
SK hynix Inc., Icheon-si, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/10 (2006.01); G06F 1/08 (2006.01); H03K 19/0185 (2006.01);
U.S. Cl.
CPC ...
G06F 1/10 (2013.01); G06F 1/08 (2013.01); H03K 19/018521 (2013.01);
Abstract
A clock distribution network includes a global clock tree and a local clock tree. When the clock distribution network is activated, the local clock tree is first activated, and the voltage levels of first and second output clock signals are set as a common mode voltage level. When the global clock tree is activated, the global clock tree generates first and second global clock signals from first and second input clock signals. The local clock tree generates the first and second output clock signals from the first and second global clock signals.