The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 21, 2025

Filed:

Dec. 01, 2022
Applicant:

Bae Systems Information and Electronic Systems Integration Inc., Nashua, NH (US);

Inventors:

Peter G. Schunemann, Hollis, NH (US);

Kevin T. Zawilski, Arlington, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
C30B 33/06 (2006.01); C30B 25/18 (2006.01); C30B 29/42 (2006.01); C30B 29/44 (2006.01); C30B 31/06 (2006.01);
U.S. Cl.
CPC ...
C30B 25/186 (2013.01); C30B 29/42 (2013.01); C30B 29/44 (2013.01); C30B 31/06 (2013.01); C30B 33/06 (2013.01);
Abstract

A method of growing large GaAs or GaP IR window slabs by HVPE, and in embodiments by LP-HVPE, includes obtaining a plurality of thin, single crystal, epitaxial-quality GaAs or GaP wafers, cleaving the wafers into tiles having ultra-flat, atomically smooth, substantially perpendicular edges, and then butting the tiles together to form an HVPE substrate larger than 4 inches for GaP, and larger than 8 inches or even 12 inches for GaAs. Subsequent HVPE growth causes the individual tiles to fuse by optical bonding into a large 'tiled' single crystal wafer, while any defects nucleated at the tile boundaries are healed, causing the tiles to merge with themselves and with the slab with no physical boundaries, and no degradation in optical quality. A dopant such as Si can be added to the epitaxial gases during the final HVPE growth stage to produce EMI shielded GaAs windows.


Find Patent Forward Citations

Loading…